i) Field of the Invention
The present invention relates to a video signal clamping circuit capable of always maintaining the DC level of digital data of digital video signals at a predetermined level after an analog-digital conversion.
ii) Description of the Related Arts
In FIG. 1, there is shown a conventional video signal clamping circuit. In this case, an input terminal IN is coupled to a buffer amplifier 1 and a clamp pulse generator circuit 7 for supplying a clamp pulse to a sample hold circuit 6. The buffer amplifier 1 is connected via a capacitor 2 to an A/D (analog-digital) converter 8 for converting a clamped analog video signal into a digital video signal b. A pair of resistor elements 3 and 4 for determining a clamp voltage are connected to a clamp voltage generator circuit 5 as a buffer means. The sample and hold circuit 6 is connected to the clamp voltage generator circuit 5 and the A/D converter 8 which in turn is coupled to an output terminal OUT.
Next, the operation of this conventional video signal clamping circuit will now be described.
As shown in FIG. 1, the analog video signal a is fed to the buffer amplifier 1 via the input terminal IN and is amplified. A DC component of an amplified analog video signal is removed by the capacitor 2. The clamp voltage determined by the resistor elements 3 and 4 is input from the clamp voltage generator circuit 5 to the sample and hold circuit 6.
On the other hand, the clamp pulse generator circuit 7 separates a horizontal synchronous signal component from the input analog video signal a and generates a clamp pulse having a proper width and timing. The generated clamp pulse is sent from the clamp pulse generator circuit 7 to the sample and hold circuit 6. The sample and hold circuit 6 holds the output of the clamp voltage generator circuit 5 at the timing of the clamp pulse output from the clamp pulse generator circuit 7. The analog video signal through the capacitor 2 is clamped at the clamp voltage output from the sample and hold circuit 6 and the clamped analog video signal is converted into the digital video signal b in the A/D converter 8. The digital video signal b is output from the output terminal OUT. A conventional video signal clamping circuit of this kind is disclosed in Japanese Patent Laid-Open No. Sho 63-176070 or the like.
Recently, with the rapid development of digital signal processing techniques, within the video signal processing field, the time base compression and extension, and even the delay and the like of the video signal are processed by using digital signals, and thus the clamping technique of the video signal to be input to the A/D converter becomes important.
For example, in a VTR (video tape recorder) or VCR (video cassette recorder), after an analog video signal is converted into a digital video signal in an A/D converter and a time base extension of a luminance signal with a wide band and a time base compression of a chrominance signal with a narrow band are carried out, a synchronizing signal is inserted to perform recording. In this case, when a DC level of the digital video signal after the A/D conversion is different from a predetermined value or is changed, an error is caused against the synchronous signal inserted in the predetermined level, or the like.
However, in the conventional video signal clamping circuit, by a change of the clamp voltage due to the variance of characteristics of circuit elements or a change of the power source voltage, the DC level of the video signal can often be shifted off a reference value. In such a case, adjustment is required every time. Further, even when the DC level of the analog video signal to be input to the A/D converter is adjusted, since the A/D converter itself contains a DC drift, the DC level of the digital signal after the A/D conversion is not always converted into the predetermined digital value.